nSys Design Systems

Company             : nSys Design Systems
Website               : www.nsysinc.com
Eligibility           : B.Tech/B.E. - Computers, Electrical, Electronics/Telecomunication, Instrumentation
Experience         : 0 - 2 Years
Location             : Delhi/NCR


nSys Design Systems
nSys Verification Suite family is the world's largest portfolio of Verification IPs. Global leaders in Semiconductor, System Houses, Networking & Storage industries use our products to accelerate their ASIC/SoC designs. We have offices in Delhi & CA.
Trainee Electronics Engineer
Experience: 0 - 2 Years
Compensation: Rupees 3,00,000
A great start with excellent growth prospects
Job Description :
* Verification of ASIC Designs
* Development of Verification IPs
* Coding of Designs / Behavioral Models in Verilog and SystemVerilog

Desired Profile :
# Sound Digital Design Fundamentals is essential
# Knowledge of microprocessors is essential
# Knowledge of Verilog/VHDL is preferred
# Knowledge of C++ & OOPS concepts is preferred
# Excellent academic track record
# Excellent communication skills

UG Qualifications:BE / B.Tech (Electrical and Electronics, Electronics and Communication, Electronics and Instrumentation)
Minimum Marks: 70%
Graduation after: 2009.
PG Qualifications:
M.E. / M.Tech (Electonics Instrumentation and Communication, Electronics and Communication, VLSI)
Minimum Marks: 70%
Post Graduation after: 2009.
Min. Class XII Marks: 75%
Min. Class X Marks: 75%


Name: Shilpa
nSys Design Systems

Email :  hr@nsysinc.com
Reference : nSys_FE


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